1. Field of the Invention
The present invention is related to semiconductor device manufacturing and more particularly to test probes for testing semiconductor integrated circuit (IC) chips.
2. Background Description
As is well known in the art, typical semiconductor integrated circuit (IC) chips have layers stacked such that layer features overlay one another to form individual devices and connect devices together. ICs are mass produced by forming an array of chips on a thin semiconductor wafer. Each array location is known as a die and each die may harbor a multilayered structure, such as an IC chip or a structure for test or alignment. The surface layer of each chip or die is typically populated by probable off-chip pads for connecting to chip power and input/output (I/O) signals.
As transistor technologies have evolved, chip features and devices have gotten smaller and smaller and have minimum dimensions that typically are well below one micrometer (1 μm) or 1 micron. Smaller chip features and devices allow IC manufacturers to integrate more function in the same chip real estate. Packing more function on each die typically means providing more and more I/O signals for each die. Each die has at least one surface pad for each I/O signal and a number of power (supply and ground) connection pads. Providing these I/O signals and supply as die are shrinking in size, therefore, drives more stringent off-chip I/O connection requirements, i.e., increasingly dense I/O pad arrays. On a typical state of the art IC wafer, for example, the surface layer of each die may be populated by several thousand connection pads. To achieve this requires ultra-fine pitch pads on very tight a pitch less than 50 microns (<50 μm).
Further, these very densely packed chip pads may also be populated with solder balls, most commonly lead-tin (PbSn) solder. The solder balls, e.g., controlled collapsible chip connections (C4s), are formed or bumped onto the pads, for example, for what is known as ball grid array (BGA) joining.
Testing these tightly packed pads with or without solder balls requires very fine, delicate, tightly-packed test probes. These densely packed state of the art probes are typically electroplated copper (Cu) tips coated with hard conductive coatings. Probing tightly-packed pads requires very precise probe tip geometry control and scalability.
Achieving necessary probe tip precision for probing ultra-fine pitch pads has proven very difficult, and therefore, expensive. Moreover, probes tend to distort mechanically with use. This distortion can make initially adequate spacing uneven. Also, copper and nickel probes have been prone to tin contamination that is especially pronounced when used on high-tin alloy solders. This contamination can cause probe misalignment and, if severe enough, probe shorts.
Thus, there is a need for a low cost probe for probing ultra-fine pitch pads and that is not sensitive to tin contamination.